/*
 * Renesas SCP/MCP Software
 * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights
 * reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef CONFIG_POWER_DOMAIN_H
#define CONFIG_POWER_DOMAIN_H

#include <rcar_scmi_id.h>

#define CONFIG_POWER_DOMAIN_CORE_CLUS0CORE0 PD_RCAR_CLUS0CORE0
#define CONFIG_POWER_DOMAIN_CORE_CLUS0CORE1 PD_RCAR_CLUS0CORE1
#define CONFIG_POWER_DOMAIN_CORE_CLUS0CORE2 PD_RCAR_CLUS0CORE2
#define CONFIG_POWER_DOMAIN_CORE_CLUS0CORE3 PD_RCAR_CLUS0CORE3
#define CONFIG_POWER_DOMAIN_CORE_CLUS1CORE0 PD_RCAR_CLUS1CORE0
#define CONFIG_POWER_DOMAIN_CORE_CLUS1CORE1 PD_RCAR_CLUS1CORE1
#define CONFIG_POWER_DOMAIN_CORE_CLUS1CORE2 PD_RCAR_CLUS1CORE2
#define CONFIG_POWER_DOMAIN_CORE_CLUS1CORE3 PD_RCAR_CLUS1CORE3
#define CONFIG_POWER_DOMAIN_CHILD_CLUSTER0  PD_RCAR_CLUSTER0
#define CONFIG_POWER_DOMAIN_CHILD_CLUSTER1  PD_RCAR_CLUSTER1

enum rcar_powerdomain_child_index {
    CONFIG_POWER_DOMAIN_CHILD_A3IR,
    CONFIG_POWER_DOMAIN_CHILD_3DGE,
    CONFIG_POWER_DOMAIN_CHILD_3DGD,
    CONFIG_POWER_DOMAIN_CHILD_3DGC,
    CONFIG_POWER_DOMAIN_CHILD_3DGB,
    CONFIG_POWER_DOMAIN_CHILD_3DGA,
    CONFIG_POWER_DOMAIN_CHILD_A2VC1,
    CONFIG_POWER_DOMAIN_CHILD_A3VC,
    CONFIG_POWER_DOMAIN_CHILD_CR7,
    CONFIG_POWER_DOMAIN_CHILD_A3VP,
    CONFIG_POWER_DOMAIN_CHILD_DDR_BKUP,
    CONFIG_POWER_DOMAIN_CHILD_ALWAYS_ON,
    CONFIG_POWER_DOMAIN_CHILD_SYSTOP,

    /* Number of defined elements */
    CONFIG_POWER_DOMAIN_CHILD_COUNT,

    CONFIG_POWER_DOMAIN_CHILD_NONE = (0xFFFFFFFFU),
};

/*!
 * \brief Types of rcar power domain.
 */
enum rcar_pd_type {
    /*! Processor. */
    RCAR_PD_TYPE_CORE,
    /*! Processor cluster. */
    RCAR_PD_TYPE_CLUSTER,
    /*! Generic device. */
    RCAR_PD_TYPE_ALWAYS_ON,
    RCAR_PD_TYPE_DEVICE,
    /*! Debug device. */
    RCAR_PD_TYPE_DEVICE_DEBUG,
    /*! System. */
    RCAR_PD_TYPE_SYSTEM,
    /*! Number of power domain types. */
    RCAR_PD_TYPE_COUNT
};

#endif /* CONFIG_POWER_DOMAIN_H */
